1. Technical Field
An embodiment of the present invention relates to a microelectronic device inter-digital capacitor (IDC). More particularly, an embodiment of the present invention relates to the use of a low-resistance IDC in connection with a high-power socket for a microelectronic device such as a processor. In particular, an embodiment of the present invention relates to a low inductance path and optionally a low resistance path for power delivery through the socket.
2. Description of Related Art
Chip packaging requires high-power sockets for devices such as processors and application-specific integrated circuits (ASICs). A processor requires a high current to enable multiple-gigahertz clock cycles to be achieved and to enable a variety of logic and memory operations to be simultaneously executed. High currents through sockets require low resistances in order to minimize power dissipation that is otherwise caused by resistance heating. Larger power dissipations in the socket result in higher socket temperatures, which in turn slow and ultimately defeat the device. Additionally, a high inductance is often generated in the power socket. Overall, the impedance (the voltage-to-current ratio) also affects the performance of the microelectronic device. An unacceptably high impedance will degrade both the signal and increase the resistance heating. When such a heating problem occurs, processor speed is slowed, or worse, the device fails with the result of lost data and lost productivity.
One way to deal with the challenges created by high current draw is to use more input/output (I/O) pins for the current draw. This allows a larger cumulative cross-sectional area to carry the power current, but the result is added cost, and even more scarce real estate on the footprint of the power socket. Further, where the number of pins added to the power dissipation load does not provide a significantly lowered resistance than the resistance of the pins in the more active regions of the processor, the effectiveness of the additional pins may not be sufficient to reduce the current flowing through a given region of the socket. Additionally, the added pins must provide an effective direct current (DC) shunt capability but they limit the I/O capability because they could otherwise carry signals instead of power.